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low skew, 1/2 differential-to-3.3v lvpecl clock generator 8737-11 datasheet 8737-11 revision c 2/13/15 1 ?2015 integrated device technology, inc. g eneral d escription the 8737-11 is a low skew, high performance differential-to-3.3v lvpecl clock generator/divider. the 8737-11 has two selectable clock inputs. the clk, nclk pair can accept most standard differential input levels. the pclk, npclk pair can accept lvpecl, cml, or sstl input levels.the clock enable isinternally synchronized to eliminate runt pulses on theoutputs during asynchronous as- sertion/deassertion of the clock enable pin. guaranteed output and part-to-part skew characteristics make the 8737-11 ideal for clock distribution applications demanding well de ned performance and repeatability. f eatures ? 2 divide by 1 differential 3.3v lvpecl outputs; 2 divide by 2 differential 3.3v lvpecl outputs ? selectable differential clk, nclk or lvpecl clock inputs ? clk, nclk pair can accept the following differential input levels: lvpecl, lvds, lvhstl, sstl, hcsl ? pclk, npclk supports the following input types: lvpecl, cml, sstl ? maximum output frequency: 650mhz ? translates any single ended input signal (lvcmos, lvttl, gtl) to lvpecl levels with resistor bias on nclk input ? output skew: 60ps (maximum) ? part-to-part skew: 200ps (maximum) ? bank skew: bank a - 20ps (maximum), bank b - 35ps (maximum) ? additive phase jitter, rms: 0.04ps (typical) ? propagation delay: 1.7ns (maximum) ? 3.3v operating supply ? 0? to 70? ambient operating temperature ? lead-free package rohs compliant b lock d iagram p in a ssignment 8737-11 20-lead tssop 6.50mm x 4.40mm x 0.92 package body g package top view v ee clk_en clk_sel clk nclk pclk npclk nc mr v cc 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 qa0 nqa0 v cc qa1 nqa1 qb0 nqb0 v cc qb1 nqb1
low skew, 1/2 differential-to- 3.3v lvpecl clock generator 8737-11 data sheet 2 revision c 2/13/15 t able 2. p in c haracteristics t able 1. p in d escriptions symbol parameter test conditions minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k r pulldown input pulldown resistor 51 k number name type description 1v ee power negative supply pin. 2 clk_en power pullup synchronizing clock enable. when high, clock outputs follow clock input. when low, q outputs are forced low, nq outputs are forced high. lvcmos / lvttl interface levels. 3 clk_sel input pulldown clock select input. when high, selects pclk, npclk inputs. when low, selects clk, nclk inputs. lvcmos / lvttl interface levels. 4 clk input pulldown non-inverting differential clock input. 5 nclk input pullup inverting differential clock input. 6 pclk input pulldown non-inverting differential lvpecl clock input. 7 npclk input pullup inverting differential lvpecl clock input. 8 nc unused no connect. 9 mr input pulldown active high master reset. when logic high, the internal dividers are reset causing the true outputs qxx to go low and the inverted outputs nqxx to go high. when logic low, the internal dividers and the outputs are enabled. lvcmos / lvttl interface levels. 10, 13, 18 v cc power positive supply pins. 11, 12 nqb1, qb1 output differential output pair. lvpecl interface levels. 14, 15 nqb0, qb0 output differential output pair. lvpecl interface levels. 16, 17 nqa1, qa1 output differential output pair. lvpecl interface levels. 19, 20 nqa0, qa0 output differential output pair. lvpecl interface levels. note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values.
revision c 2/13/15 8737-11 data sheet 3 low skew, 1/2 differential-to- 3.3v lvpecl clock generator t able 3a. c ontrol i nput f unction t able t able 3b. c lock i nput f unction t able inputs outputs mr clk_en clk_sel selected source qa0, qa1 nqa0, nqa1 qb0, qb1 nqb0, nqb1 1 x x x low high low high 0 0 0 clk, nclk disabled; low disabled; high disabled; low disabled; high 0 0 1 pclk, npclk disabled; low disabled; high disabled; low disabled; high 0 1 0 clk, nclk enabled enabled enabled enabled 0 1 1 pclk, npclk enabled enabled enabled enabled after clk_en switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown if figure 1. in the active mode, the state of the outputs are a function of the clk , nclk and pclk, npclk inputs as described in table 3b. inputs outputs input to output mode polarity clk or pclk nclk or npclk qax nqax qbx nqbx 0 0 low high low high differential to differential non inverting 1 1 high low high low differential to differential non inverting 0 biased; note 1 low high low high single ended to differential non inverting 1 biased; note 1 high low high low single ended to differential non inverting biased; note 1 0 high low high low single ended to differential inverting biased; note 1 1 low high low high single ended to differential inverting note 1: please refer to the application information section, ?iring the differential input to accept single ended levels? f igure 1. clk_en t iming d iagram nclk, npclk clk, pclk clk_en nqa0, nqa1, nqb0, nqb1 qa0, qa1, qb0, qb1
low skew, 1/2 differential-to- 3.3v lvpecl clock generator 8737-11 data sheet 4 revision c 2/13/15 t able 4a. p ower s upply dc c haracteristics , v cc = 3.3v?%, t a = 0? to 70? t able 4b. lvcmos / lvttl dc c haracteristics , v cc = 3.3v?%, t a = 0? to 70? t able 4c. d ifferential dc c haracteristics , v cc = 3.3v?%, t a = 0? to 70? symbol parameter test conditions minimum typical maximum units v cc positive supply voltage 3.135 3.3 3.465 v i ee power supply current 50 ma symbol parameter test conditions minimum typical maximum units v ih clk_en, clk_sel, mr 2 3.765 v v il clk_en, clk_sel, mr -0.3 0.8 v i ih input high current clk_en v in = v cc = 3.465v 5 a clk_sel, mr v in = v cc = 3.465v 150 ? i il input low current clk_en v in = 0v, v cc = 3.465v -150 ? clk_sel,mr v in = 0v, v cc = 3.465v -5 ? symbol parameter test conditions minimum typical maximum units i ih input high current nclk v in = v cc = 3.465v 5 a clk v in = v cc = 3.465v 150 ? i il input low current nclk v in = 0v, v cc = 3.465v -150 ? clk v in = 0v, v cc = 3.465v -5 ? v pp peak-to-peak input voltage 0.15 1.3 v v cmr common mode input voltage; note 1, 2 v ee + 0.5 v cc - 0.85 v note 1: for single ended applications, the maximum input voltage for clk, nclk is v cc + 0.3v. note 2: common mode voltage is de ned as v ih . a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuous current 50ma surge current 100ma package thermal impedance, ja 73.2?/w (0 lfpm) storage temperature, t stg -65? to 150? note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress speci cations only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac charac- teristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
revision c 2/13/15 8737-11 data sheet 5 low skew, 1/2 differential-to- 3.3v lvpecl clock generator t able 5. ac c haracteristics , v cc = 3.3v?%, t a = 0? to 70? t able 4d. lvpecl dc c haracteristics , v cc = 3.3v?%, t a = 0? to 70? symbol parameter test conditions minimum typical maximum units f max output frequency 650 mhz t pd propagation delay; note 1 clk, nclk ? 650mhz 1.3 1.7 ns pclk, npclk 1.2 1.6 ns tsk(o) output skew; note 2, 4 60 ps tsk(b) bank skew; note 4 bank a 20 ps bank b 35 ps tsk(pp) part-to-part skew; note 3, 4 200 ps tjit buffer additive phase jitter, rms; refer to additive phase jitter section, note 5 0.04 ps t r output rise time 20% to 80% @ 50mhz 300 700 ps t f output fall time 20% to 80% @ 50mhz 300 700 ps odc output duty cycle 48 50 52 % all parameters measured at 500mhz unless noted otherwise. the cycle-to-cycle jitter on the input will equal the jitter on the output. the part does not add jitter. note 1: measured from the differential input crossing point to the differential output crossing point. note 2: de ned as skew between outputs at the same supply voltage and with equal load conditions. measured at the output differential cross points. note 3: de ned as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross points. note 4: this parameter is de ned in accordance with jedec standard 65. note 5: driving only one input clock. symbol parameter test conditions minimum typical maximum units i ih input high current v in = v cc = 3.465v 150 ? v in = v cc = 3.465v 5 a i il input low current v in = 0v, v cc = 3.465v -5 ? v in = 0v, v cc = 3.465v -150 ? v pp peak-to-peak input voltage 0.3 1 v v cmr common mode input voltage; note 1, 2 v ee + 1.5 v cc v v oh output high voltage; note 3 v cc - 1.4 v cc - 0.9 v v ol output low voltage; note 3 v cc - 2.0 v cc - 1.7 v v swing peak-to-peak output voltage swing 0.65 1.0 v note 1: common mode voltage is de ned as v ih . note 2: for single ended applications, the maximum input voltage for pclk, npclk is v cc + 0.3v. note 3: outputs terminated with 50 to v cc - 2v.
low skew, 1/2 differential-to- 3.3v lvpecl clock generator 8737-11 data sheet 6 revision c 2/13/15 a dditive p hase j itter input/output additive phase jitter at 155.52mhz = 0.04ps typical 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1m 10m 100m the spectral purity in a band at a speci c offset from the fun- damental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the speci ed plot in many applications. phase noise is de ned as the ratio of the noise power present in a 1hz band at a speci ed offset from the fun- damental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the as with most timing speci cations, phase noise measurements have issues. the primary issue relates to the limitations of the equipment. often the noise oor of the equipment is higher than the noise oor of the device. this is illustrated above. the 1hz band to the power in the fundamental. when the required offset is speci ed, the phase noise is called a dbc value, which simply means dbm at a speci ed offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. device meets the noise oor of what is shown, but can actually be lower. the phase noise is dependant on the input source and measurement equipment. o ffset f rom c arrier f requency (h z ) ssb p hase n oise dbc/h z
revision c 2/13/15 8737-11 data sheet 7 low skew, 1/2 differential-to- 3.3v lvpecl clock generator p arameter m easurement i nformation p art - to -p art s kew p ropagation d elay o utput r ise /f all t ime d ifferential i nput l evel o utput s kew 3.3v o utput l oad ac t est c ircuit o utput d uty c ycle /p ulse w idth /p eriod
low skew, 1/2 differential-to- 3.3v lvpecl clock generator 8737-11 data sheet 8 revision c 2/13/15 a pplication i nformation figure 2 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref ~ v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the r atio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the inpu t clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. f igure 2. s ingle e nded s ignal d riving d ifferential i nput the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, termi- nating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 3a and 3b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for lvpecl o utputs f igure 3b. lvpecl o utput t ermination f igure 3a. lvpecl o utput t ermination w iring the d ifferential i nput to a ccept s ingle e nded l evels
revision c 2/13/15 8737-11 data sheet 9 low skew, 1/2 differential-to- 3.3v lvpecl clock generator f igure 4c. clk/nclk i nput d riven by 3.3v lvpecl d river f igure 4b. clk/nclk i nput d riven by 3.3v lvpecl d river f igure 4d. clk/nclk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 4a to 4e show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are f igure 4a. clk/nclk i nput d riven by lvhstl d river examples only. please consult with the vendor of the driver component to con rm the driver termination requirements. for example in figure 4a, the input termination applies for lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk f igure 4e. clk/ n clk i nput d riven by 3.3v lvpecl d river with ac c ouple zo = 50 ohm r3 125 hiperclocks clk nclk 3.3v r5 100 - 200 3.3v r2 84 3.3v r6 100 - 200 input r5,r6 locate near the driver pin. zo = 50 ohm r1 84 r4 125 c2 lvpecl c1 zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v
low skew, 1/2 differential-to- 3.3v lvpecl clock generator 8737-11 data sheet 10 revision c 2/13/15 lvpecl c lock i nput i nterface the pclk /npclk accepts lvpecl, cml, sstl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 5a to 5e show interface examples for the pclk/npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to con rm the driver termination requirements. f igure 5a. pclk/npclk i nput d riven by a cml d river f igure 5b. pclk/npclk i nput d riven by an sstl d river f igure 5c. pclk/npclk i nput d riven by a 3.3v lvpecl d river f igure 5d. pclk/npclk i nput d riven by a 3.3v lvds d river hiperclocks pclk npclk pclk/npclk 3.3v r2 50 r1 50 3.3v zo = 50 ohm cml 3.3v zo = 50 ohm pclk/npclk 2.5v zo = 60 ohm sstl hiperclocks pclk npclk r2 120 3.3v r3 120 zo = 60 ohm r1 120 r4 120 2.5v f igure 5e. pclk/npclk i nput d riven by a 3.3v lvpecl d river with ac c ouple 3.3v r5 100 - 200 3.3v 3.3v hiperclocks pclk npclk r1 125 pclk/npclk r2 125 r3 84 c1 c2 zo = 50 ohm r4 84 zo = 50 ohm r6 100 - 200 3.3v lvpecl c2 r2 1k r5 100 zo = 50 ohm 3.3v 3.3v c1 r3 1k lvds r4 1k hiperclocks pclk npclk r1 1k zo = 50 ohm 3.3v pclk/npclk 3.3v hiperclocks pclk npclk r2 84 r3 125 input zo = 50 ohm r4 125 r1 84 lvpecl 3.3v 3.3v zo = 50 ohm
revision c 2/13/15 8737-11 data sheet 11 low skew, 1/2 differential-to- 3.3v lvpecl clock generator p ower c onsiderations this section provides information on power dissipation and junction temperature for the 8737-11. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 8737-11 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i cc_max = 3.465v * 50ma = 173.25mw ? power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 4 * 30mw = 120mw total power _max (3.465v, with all outputs switching) = 173.25mw + 120mw = 293.25mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for the devices is 125?. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6?/w per table 6 below. therefore, tj for an ambient temperature of 70? with all outputs switching is: 70? + 0.293w * 66.6?/w = 89.5?. this is well below the limit of 125?. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air ow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 114.5?/w 98.0?/w 88.0?/w multi-layer pcb, jedec standard test boards 73.2?/w 66.6?/w 63.5?/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 6. t hermal r esistance ja for 20- pin tssop, f orced c onvection
low skew, 1/2 differential-to- 3.3v lvpecl clock generator 8737-11 data sheet 12 revision c 2/13/15 3. calculations and equations. lvpecl output driver circuit and termination are shown in figure 6. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cc - 2v. ? for logic high, v out = v oh_max = v cc_max ? 0.9v (v cc_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cc_max ? 1.7v (v cc_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ?(v cc_max - 2v))/r l ] * (v cc_max - v oh_max ) = [(2v - (v cc_max - v oh_max )) /r l ] * (v cc_max - v oh_max ) = [(2v - 0.9v)/50 ] * 0.9v = 19.8mw pd_l = [(v ol_max ?(v cc_max - 2v))/r l ] * (v cc_max - v ol_max ) = [(2v - (v cc_max - v ol_max )) /r l ] * (v cc_max - v ol_max ) = [(2v - 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 6. lvpecl d river c ircuit and t ermination
revision c 2/13/15 8737-11 data sheet 13 low skew, 1/2 differential-to- 3.3v lvpecl clock generator r eliability i nformation t ransistor c ount the transistor count for 8737-11 is: 510 t able 7. ja vs . a ir f low t able for 20 l ead tssop ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 114.5?/w 98.0?/w 88.0?/w multi-layer pcb, jedec standard test boards 73.2?/w 66.6?/w 63.5?/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
low skew, 1/2 differential-to- 3.3v lvpecl clock generator 8737-11 data sheet 14 revision c 2/13/15 p ackage o utline - g s uffix for 20 l ead tssop t able 8. p ackage d imensions reference document: jedec publication 95, mo-153 symbol millimeters minimum maximum n20 a -- 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 6.40 6.60 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa -- 0.10
revision c 2/13/15 8737-11 data sheet 15 low skew, 1/2 differential-to- 3.3v lvpecl clock generator t able 9. o rdering i nformation part/order number marking package shipping packaging temperature 8737ag-11lf ics8737ag11l 20 lead ?ead-free tssop tube 0? to 70? 8737AG-11LFT ics8737ag11l 20 lead ?ead-free tssop tape & reel 0? to 70? note: parts that are ordered with an ?f suf x to the part number are the pb-free con guration and are rohs compliant.
low skew, 1/2 differential-to- 3.3v lvpecl clock generator 8737-11 data sheet 16 revision c 2/13/15 revision history sheet rev table page description of change date a 3 updated figure 1, clk_en timing diagram. 10/17/01 a 3 revised figure 1, clk_en timing diagram. 10/31/01 a 8 added termination for lvpecl outputs section. 6/3/02 a 12 6 7 pin description table - revised mr description. 3.3v output load test circuit diagram, revised vee equation from ?1.3v ?0.135v to ?-1.3v ?0.165v? revised output rise/fall time diagram. 8/19/02 b t1 t2 t5 2 2 4 5 6 8 9 10 pin description table - revised mr description. pin characteristics table - changed c in 4pf max. to 4pf typical. absolute maximum ratings, updated output rating. ac characteristics table - added additive phase jitter. added additive phase jitter section. updated lvpecl output termination drawings. added differential clock input interface section. added lvpecl clock input interface section. updated format throughout the data sheet. 2/3/04 b t9 1 15 added lead-free bullet to features section. added lead-free marking to ordering information table. 2/10/05 b t9 1 15 features section - deleted bullet, ?ndustrial temperature information available upon request. ordering information table - added lead-free note. 3/18/05 c t4d 5 11 - 12 lvpecl dc characteristics table -corrected v oh max. from v cc - 1.0v to v cc - 0.9v; and v swing max. from 0.9v to 1.0v. power considerations - corrected power dissipation to re ect v oh max in table 4d. 4/13/07 c t9 15 17 updated datasheets header/footer with idt from ics. removed ics pre x from part/order number column. added contact page. 8/9/10 c t9 15 ordering information - removed leaded devices - pdn cq-13-02 2/13/15
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